The invention relates generally to a semiconductor device and a method for manufacturing a semiconductor device. More specifically, the invention relates to a technique that is effective for ensuring a sufficient process margin to enable the formation of a fine pattern in a peripheral circuit region. The invention includes forming an anti-reflective layer with a varying thickness in a peripheral circuit region as compared to a cell region, and then over-etching the anti-reflective layer in the peripheral circuit region. The invention is capable of improving the data processing speed of a semiconductor device to thereby increase the device efficiency.
With trends in size reduction according to the decreasing design rule of DRAM processes, transistors formed in a peripheral circuit region also should be reduced in size. In reality, however, an isolation pattern in the peripheral circuit region has a short process margin, compared with a dense pattern in a cell region, so it is difficult to form a fine pattern in the peripheral circuit region.
This difficulty arises during a pattern formation process in which a broad area of the isolation pattern in the peripheral circuit region is etched. This causes the etch loading effect to occur, and by-products are deposited on the sides of etched semiconductor structures.